A Dynamically Tunable Memory Hierarchy

@article{Balasubramonian2003ADT,
  title={A Dynamically Tunable Memory Hierarchy},
  author={Rajeev Balasubramonian and David H. Albonesi and Alper Buyuktosunoglu and Sandhya Dwarkadas},
  journal={IEEE Trans. Computers},
  year={2003},
  volume={52},
  pages={1243-1258}
}
The widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy that leverages repeater insertion to dynamically trade off size for speed and power consumption on a per-application phase basis using a novel configuration management algorithm. In comparison to a conventional design that is fixed at a single design point targeted to the average application, the… CONTINUE READING

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