A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops

@article{Chiu2010ADP,
  title={A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops},
  author={Wei-Hao Chiu and Yu-Hsiang Huang and Tsung-Hsien Lin},
  journal={IEEE Journal of Solid-State Circuits},
  year={2010},
  volume={45},
  pages={1137-1149}
}
This paper presents a fast-locking technique for phase-locked loops (PLLs). In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process. The detected phase error is then coarsely compensated by dynamically changing the divide ratio of the frequency divider. The proposed method allows the PLL to maintain a small phase error throughout the frequency acquisition process, thereby reducing… CONTINUE READING
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