A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs

@article{Vera2011ADD,
  title={A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs},
  author={G. Alonzo Vera and Marios S. Pattichis and James Lyke},
  journal={Int. J. Reconfig. Comp.},
  year={2011},
  volume={2011},
  pages={518602:1-518602:19}
}
In FPGA embedded systems, designers usually have to make a compromise between numerical precision and logical resources. Scientific computations in particular, usually require highly accurate calculations and are computing intensive. In this context, a designer is left with the task of implementing several arithmetic cores for parallel processing while supporting high numerical precision with finite logical resources. This paper introduces an arithmetic architecture that uses runtime partial… CONTINUE READING
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