A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process

Abstract

A 0.2-to-4GHz PLL generates the clock for an SoC in a 65nm CMOS process. The PLL uses dual-oxide devices operating in different voltage domains to generate a clock with a wide range of output frequencies and low jitter. The measured rms period jitter is 1.5ps at 2GHz and total power consumed from both the 1.0V and 1.8V supplies is 15mW. 
DOI: 10.1109/ISSCC.2007.373417

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Cite this paper

@article{Desai2007AD0, title={A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process}, author={Shaishav Desai and Pradeep Trivedi and Vincent Von Kanael}, journal={2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers}, year={2007}, pages={308-605} }