A Dual PFD Phase Rotating Multi-Phase PLL for 5Gbps PCI Express Gen2 Multi-Lane Serial Link Receiver in 0.13um CMOS

A dual phase frequency detector phase-locked loop (PLL) architecture for multi-lane 5 Gbps serial link receiver is demonstrated using 0.13 mum CMOS. The PLL's 8 multiphase clocks can be rotated altogether digitally with respect to a single fixed phase clock from a main PLL. The phase step resolution is 1/15 of a unit bit interval and the rotation is… CONTINUE READING