A Dual-Junction Single-Photon Avalanche Diode in 130-nm CMOS Technology

@article{Henderson2013ADS,
  title={A Dual-Junction Single-Photon Avalanche Diode in 130-nm CMOS Technology},
  author={R. Henderson and E. Webster and L. Grant},
  journal={IEEE Electron Device Letters},
  year={2013},
  volume={34},
  pages={429-431}
}
A dual-junction single-photon avalanche diode structure is reported in a 130-nm low-voltage CMOS technology. The device comprises two stacked avalanche multiplication regions with virtual guard ring constructions. An 8.6- μm-diameter p-well is placed within a 12.3- μm-diameter deep n-well. At 3-V excess bias, the junctions operate with median dark count rates of 10 and 5 kHz and photon detection efficiencies of 32% at 450 nm and 29% at 670 nm, respectively. We demonstrate that the junction at… Expand

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