A centraiized wireless ATM LAN consists of a base station and multiple mobile stations. Since they share one cornrnon transmission medium, medium access control (MAC) is needed to coordinate the order of transmission. To maintain features of BISDN, the MAC has to consider a connection's Quality of Service while ailocating resources. One of the proposed MAC protocols for providing wireless multiservices is called distributed fair queuing (DFQ). DFQ is a TDMA-based MAC scheme which dynamically performs per-ceïi scheduling based on the celi's priority. Success of implementing DFQ largely depends on scheduluig efficiency. A software scheduler wili not be fast enough for this real time task. Therefore, an efficient hardware scheduler is required. The major theme of this thesis is to design such a scheduler. As a second theme, it considers issues of WATM LAN system design and proposes a system architecture for implernenting MAC functions using existing commercial ATM cards. I would like to thank my supervisor Prof. Leon-Garcia for providing guidance on the research direction and providing assistance, suggestions and consultation for problems throughout the research. 1 would also like to thank many fellow students in the Communication Group who provided valuable assistance in various ways: Richard Kautz and Seyed Mohammed Ali Arad, who workeci on the same project, provided many materials and references on the wireless ATM; Massoud Reza Hashemi had many inputs on the design of the wrap sequencer; Massoud Hadjiahmad provided much information on hardware parts suitable to be used in building our MAC board; Keith Chow provides information on the ATM products. 1 would also like to thank Prof. Paul Chow and his student Vineet Joshi for implementing and testing the Wrap Sequencer in their FPGA board.