A Digital Real Time Image Demosaicking Implementation for High Definition Video Cameras


This paper describes a digital real time image demosacking implementation for high definition video cameras. It comprises one buffer for three pixel rows and one interpolator based on bilinear interpolation. It has been implemented with HDL-Verilog and mapped onto Virtex-4 XC4VLX25 from Xilinx; for a clock frequency of 150 MHZ, its throughput is 72 frames per second. This implementation may be used as an intellectual property for FPGA's or SoC.

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