A Digital PLL Using Oversampling Delta-Sigma TDC


A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter (ΔΣTDC) is presented. This ΔΣTDC adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed ΔΣTDC consumes 0.519 mW at a supply of 1.1 V, and… (More)
DOI: 10.1109/TCSII.2016.2530904


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@article{Wei2016ADP, title={A Digital PLL Using Oversampling Delta-Sigma TDC}, author={Chih-Lu Wei and Shen-Iuan Liu}, journal={IEEE Transactions on Circuits and Systems II: Express Briefs}, year={2016}, volume={63}, pages={633-637} }