A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing

@article{Dutta2006ADM,
  title={A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing},
  author={H. Dutta and F. Hannig and J. Teich and B. Heigl and Heinz Hornegger},
  journal={IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)},
  year={2006},
  pages={331-340}
}
  • H. Dutta, F. Hannig, +2 authors Heinz Hornegger
  • Published 2006
  • Computer Science
  • IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
  • Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a state-of-the-art algorithm in medical imaging, which falls in the class of 2D adaptive filter algorithms. In this paper, we propose a semi-automatic mapping methodology for the generation of hardware accelerators for such a generic class of adaptive filtering applications in image processing. The final architecture deliver… CONTINUE READING
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