Electronic cochlea models are used for physiological modeling as well as in many signal processing tasks such as pitch detection and speech recognition. Hardware based electronic cochlea systems offer improved performance, lower power consumption and smaller footprint over software based systems. Field Programmable Gate Arrays (FPGA) provide a means to reconfigure cochlea systems so that they can serve as the front-end signal processing for different models of the auditory nervous system. This study is concerned with the efficient implementation of cochlea filters in digital hardware. It is demonstrated that computations in the low frequency sections of the cochlea cascade can be reduced by employing decimation. High performance FPGA-based implementation of cochlea systems with different levels of decimation were developed. This study also introduces a sequential processing architecture and evaluates the accuracy, performance and resource utilization of different implementations using fixed-point and dual fixed-point arithmetic. A baseline cochlea employing a sequential processing unit was developed and could achieve a maximum processing rate of 933 kHz. A variable decimation cochlea was developed to speed up the computations of the cochlea systems and provided an efficient method to evaluate the aliasing and performance tradeoffs of a cochlea system by varying decimation used. To demonstrate the efficiency of dual fixed-point arithmetic, cochlea systems using dual fixed-point arithmetic were implemented and compared with fixed-point systems. i The resulting decimated implementations achieved 173% and 49% speedups with cutoff values of -60 dB and -80 dB respectively. The DFX designs had a 20-30 dB higher signal to noise ratio than the fixed-point designs. Measurements show that these DFX implementations used 24.9% more logic resources but the number and size of the multipliers used in both fixed-point and DFX implementations were the same.