Corpus ID: 15070747

A Cost Effective Design of Reversible Single Precision Floating Point Multiplier

@inproceedings{Malathi2013ACE,
  title={A Cost Effective Design of Reversible Single Precision Floating Point Multiplier},
  author={Malathi and Akshaya Venugopal and Pavithra Sarathy},
  year={2013}
}
The emerging computing technologies like quantum computing, optical computing, low power computing etc. make use of reversible logic. Also applications like image processing and signal processing make use of floating point (FP) multiplications as the major operations. In this paper we propose the design of a low power, cost effective reversible floating point multiplier for such applications. The proposed design is comparable with the reversible FP multipliers discussed in the literature so far… Expand
1 Citations

Figures and Tables from this paper

References

SHOWING 1-10 OF 19 REFERENCES
Design of a reversible single precision floating point multiplier based on operand decomposition
Design of a reversible floating-point adder architecture
Novel Reversible Multiplier Architecture Using Reversible TSG Gate
  • H. Thapliyal, M. Srinivas
  • Computer Science
  • IEEE International Conference on Computer Systems and Applications, 2006.
  • 2006
Novel Reversible Multiplier Circuit in Nanotechnology
Novel Reversible `TSG' Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU
  • H. Thapliyal, M. Srinivas
  • Computer Science, Mathematics
  • 2005 5th International Conference on Information Communications & Signal Processing
  • 2005
Reversible logic synthesis for minimization of full-adder circuit
An Algorithm for Synthesis of Reversible Logic Circuits
Efficient adder circuits based on a conservative reversible logic gate
...
1
2
...