This paper describes a Spice-compatible circuit simulation model of submicron LDD MOS devices. It includes an enhanced model of our previous drain current characteristics (UNIMOS) and a new analytical substrate current model. For the drain current characteristics, new features of our previous model has been added for achieving good accuracy and convergency. In addition, the two-dimensional electric field distribution during impact ionization which has much more physical meaning is Considered for developing the hot electron model. Thus, a new and accurate substrate current model is proposed based on the so called effective electric field, instead of the conventional peak electric field concept used by the lucky-electron (LE) theory. Comparison of the modeled results with those of experiment shows excellent match for a wide range of device channel lengths and bias conditions. Introduction In recent years, three basic models needed for circuit simulation in Spice are the dc(1-V), ac (C-V) and the hot carrier models. The first two MOS device models in Spice have been developed for years [l]. The Berkeley SPICE MOS models which have been evolved from LEVEL 1, 2 3 to a reccnt LEVEL 4BSIM  version has shown wide applications for conventional MOS devices. However, the effort put on the hot carrier model is not sufficient . It is also known that the substrate currcnt,IB, can be used for monitoring Uie hot carrier effect and also for analyzing Ihe device or circuit hot carrier reliability in VLSI design. Owing to the lirnitation of Ihe Ig model based on the conventional LE concept, a substrate current model is essential for developing or optimizing hot carrier resistant devices or circiiits using Spice as an aid. Continuing efforts will be made to improve currently used dc models and the inclusion of the substrate current in circuit simulation using Spice. In modeling the substrate current of,a conventional MOS device, the following form  based on the Lucky-Electron concept is widely used: in which E m = ( V ~ ~ V ~ s a t ) / l d is generally considertd as the maximum electric field within a device. The electric field inside devices is a complicated 2-D distribution and the substrate current should be the overdl result of the field distribution. As a consequence, the surface peak electric field can not always accurately modcling the substrate current using (l), particularly for LDD-slructure devices. The present Spice model includes a consistent set of ID and IB models. An enhanced version of our previous ID model will be first described. In addition, a new substrate current model based on the 2D effective electric field concept will be demonstrated. Unimos-Plus : An Enhanced Submicron LDD MOS Device Drdn-current Model An enhanced version of the drain current characteristics of small gcometry LDD MOSFETs was first developed based on our previous models in [3,5] and a newly-developed optimization algorithm. The expressions achieved for the drain currents hold in the weak inversion, strong inversion and saturation regimes of opcration. Fig.1 shows h e schematic diagrani of an LDD MOS dcvicc, in which Uie dcvice is considered to be an intrinsic MOS device in series with two voltage dependent drain-and-source series rcsistanccs. These two resistances are derived as functions of gate voltage and drain voltagcs. For the former, Ihe total drain-and-source series resistance is characterized as functions of the gate voltages. For the latter, it has becn incorporated into the mobility degradation term, eq.(Al). so that accurate I-V characteristics in the linear region can be achieved. In the device saturation region of operation, the dctermination of saturation voltage, VDSAT. is rather important which will affect the accuracy of the I-V curves and also the continuity of these curves. Fig.3 shows the resultant V D ~ ~ ~ at various gate voltages. Verification of the I-V model is given in Fig.4 which gives quite good match with experimental data. Discontinuity of the I-V curves at the near threshold region in the Spice L E V E k 3 has been solved by adding only two empirical factors a and IO. as shown in eq.(A3). Table 1. Both paramctcrs can be determined experimcntally. Smooth transition at the near threshold (Fig. 5 ) is obtained which can speed up the convergence in circuit simulation and hence saves CPU time. Only 12 model paramefers are uscd to fully adapt the small geometry I-V models to a given process which is much less than the BSIM model. Benckmark test of a ring oscillator shows a 30% savings in CPU time by comparing with Spice LEVEL=3. Several major improvements in the newly developed LDD MOS device drain current model include: (1) a gate voltage and drain voltage dependent properties of the drain-source series resistance, (2) experimental determination of the saturation voltages, and (3) a very accurate subthreshold model. A New Substrate Current Model Based on the aforementioned effective eleclric ficld concept, an improved substrate current can be expressed as Here, Eeff(VDs-qv,sAT)fid is the eflective electric field within devices, which is bias dependent. Id is the impact ionization length. VDSAT is the saturation voltage which can be extracted from experimental data as illustrated in the previous section. The impact ionization coefficients adopt the values from , and are treated as fixed values in this study. Rearranging (2b), we can obtain another Eeff expression which gives Here, ID and Ig are the mcasured drain and subsuatc currents. respcctively. Id andq can bc uniquely defined using extraction of (3). Fig. 6 shows the linear relationship between E,[[ and VDS. ~ V D ~ ~ ~ and Id are found to be function of VGs. as shown in Fig.7. Fig. 8 shows a verification of the modelcd substrate currents with experimental data. Excellent match can be achieved for different channel Icngths and bias conditions.. In summary, we add a ncw LDD MOS lransistor substratc current modcl in Spice in addition to the drain current model. For the drain current characteristics, new features and enhancemenls of our previous model have been addcd for achicving accuracy and good convcrgcncy. For Uie substrate current, an accurate model and the associated paramcter extractions is proposed bascd on the so called effective eleclric field, instead of h e conventional peak electric field used by the lucky-clcctron (LE) concept. Comparison of thc modeled results with thosc of experiment shows exccllent match for a wide range of device channcl lengths and bias conditions. The dcvclopcd analytical modcl can be used for circuit level reliability simulation  in the currciil LDD MOS dcvice technology. Acknowledgements The financial support in part by thc Nationai Science Council under contract no. 8 I-0404-E009-620 is gratefully acknowlcdgcd.