A Configurable Pixel Cache for Fast Image Generation

@article{Goris1987ACP,
  title={A Configurable Pixel Cache for Fast Image Generation},
  author={Andy Goris and Bob Fredrickson and Harold L. Baeverstad},
  journal={IEEE Computer Graphics and Applications},
  year={1987},
  volume={7},
  pages={24-32}
}
This article describes an approach to fast image generation that uses a high-speed serial scan converter, a somewhat slower frame buffer, and a pixel cache to match the bandwidth between the two. Cache hit rates are improved by configuring the cache to buffer either 4 × 4 or 16 × 1 tiles of frame memory, depending on the type of operation being performed. For line drawing, the implenmention discribed can process 300,000 30-pixel vectors per second. For shaded polygons, the system can fill 16… CONTINUE READING

References

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Architectures and Algorithms for Parallel Updates of Raster Scan Displays, doctoral dissertation

  • S. Gupta
  • 1981

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