A Comprehensive Hdl Model of a Line Associative Register Based Architecture

Abstract

Modern processor architectures suffer from an ever increasing gap between processor and memory performance. The current memory-register model attempts to hide this gap by a system of cache memory. Line Associative Registers(LARs) are proposed as a new system to avoid the memory gap by pre-fetching and associative updating of both instructions and data. This thesis presents a fully LAR-based architecture, targeting a previously developed instruction set architecture. This architecture features an execution pipeline supporting SWAR operations, and a memory system supporting the associative behavior of LARs and lazy writeback to memory.

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Cite this paper

@inproceedings{Sparks2013ACH, title={A Comprehensive Hdl Model of a Line Associative Register Based Architecture}, author={Matthew A Sparks}, year={2013} }