A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths

@article{Toms2010ACS,
  title={A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths},
  author={William B. Toms and David A. Edwards},
  journal={2010 10th International Conference on Application of Concurrency to System Design},
  year={2010},
  pages={24-34}
}
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic can be complex and expensive. This paper presents a complete synthesis flow that generates self-timed combinational networks from conventional Boolean networks. The Boolean network is partitioned into small function blocks which are then synthesised using self-timed techniques. The procedure employs relaxation optimisations to distribute the overheads… CONTINUE READING
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