Corpus ID: 16637244

A Complementary GaAs 53-bit Parallel Array Floating Point Multiplier

@inproceedings{Kim2007ACG,
  title={A Complementary GaAs 53-bit Parallel Array Floating Point Multiplier},
  author={Hyungwon Kim},
  year={2007}
}
A complementary gallium-arsenide (CGaAs) 53-bit parallel array floating point multiplier is presented. The design uses Motorola's 0.5µm C-GaAs process. A conventional Wallace tree of 42 compressors is used to generate the product terms and a dynamic Ling carry select adder is utilized in the final addition to form the final mantissa. An internal latch allows the design to use a two cycle pipelined scheme. The Wallace tree has a simulated delay of 870ps and consumes about 5.2W of power. The… Expand
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