A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures

@article{Sih1993ACS,
  title={A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures},
  author={Gilbert C. Sih and Edward A. Lee},
  journal={IEEE Trans. Parallel Distrib. Syst.},
  year={1993},
  volume={4},
  pages={175-187}
}
This paper presents a compile-time scheduling heuristic called dynamic level scheduling, which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto heterogeneous processor architectures with limited or possibly irregular interconnection structures. This technique uses dynamicallychanging priorities to match tasks with processors at each step, and schedules over both spatial and temporal dimensions to eliminate shared resource… CONTINUE READING
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