A Compact Low Voltage CMOS Four-Quadrant Analog Multiplier

Abstract

In this paper, a compact low-voltage CMOS fourquadrant analog multiplier is proposed. The proposed circuit is obtained by rearranging circuit topology of a recently reported multiplier which is unpractical since the circuit topology itself needs an ideal voltage reference to form a multiplication function. By doing so, the ideal voltage reference is no longer required leading to achieve a new multiplier circuit with real compactness. Simulated results using PSPICE for 0.35 m CMOS process show that main performances of the proposed multiplier, including linearity, bandwidth and power consumption, are successfully improved.

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Cite this paper

@inproceedings{KiatwarinACL, title={A Compact Low Voltage CMOS Four-Quadrant Analog Multiplier}, author={N. Kiatwarin} }