A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

  title={A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT},
  author={Ze-ke Wang and Xue Liu and Beixin Julie He and Feng Yu},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
We present an efficient combined single-path delay commutator-feedback (SDC-SDF) radix-2 pipelined fast Fourier transform architecture, which includes log2 N - 1 SDC stages, and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers. Thus, the required number of complex multipliers is reduced to log4 N - 0.5, compared with log2 N - 1 for the… CONTINUE READING
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A high-speed low-complexity modified radix-25 FFT processor for high rate WPAN applications

  • T. Cho, S. Tsai, H. Lee
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