A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

@article{Wang2015ACS,
  title={A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT},
  author={Ze-ke Wang and Xue Liu and Beixin Julie He and Feng Yu},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2015},
  volume={23},
  pages={973-977}
}
We present an efficient combined single-path delay commutator-feedback (SDC-SDF) radix-2 pipelined fast Fourier transform architecture, which includes log2 N - 1 SDC stages, and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers. Thus, the required number of complex multipliers is reduced to log4 N - 0.5, compared with log2 N - 1 for the… CONTINUE READING
Highly Cited
This paper has 29 citations. REVIEW CITATIONS

From This Paper

Topics from this paper.

Citations

Publications citing this paper.
Showing 1-10 of 21 extracted citations

References

Publications referenced by this paper.
Showing 1-10 of 24 references

A high-speed low-complexity modified radix-25 FFT processor for high rate WPAN applications

  • T. Cho, S. Tsai, H. Lee
  • IEEE Trans. Very Large Scale Inegr. (VLSI) Syst…
  • 2013
1 Excerpt

Similar Papers

Loading similar papers…