A Combined Decimal and Binary Floating-Point Multiplier

@article{Tsen2009ACD,
  title={A Combined Decimal and Binary Floating-Point Multiplier},
  author={Charles Tsen and Sonia Gonzalez-Navarro and Michael J. Schulte and Brian J. Hickmann and Katherine Compton},
  journal={2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors},
  year={2009},
  pages={8-15}
}
In this paper, we describe the first hardware design of a combined binary and decimal floating-point multiplier, based on specifications in the IEEE 754-2008 Floating-point Standard. The multiplier design operates on either (1) 64-bit binary encoded decimal floating-point (DFP) numbers or (2) 64-bit binary floating-point (BFP) numbers. It returns properly rounded results for the rounding modes specified in IEEE 754-2008. The design shares the following hardware resources between the two… CONTINUE READING
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