A Combined Approach of IVC and GR for Leakage Power Reduction in CMOS VLSI Digital Circuit

Abstract

In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap for Semiconductor (ITRS). Leakage power decreases battery life for the entire portable battery operated device such as mobile phones, laptop and cam coder… (More)

Topics

Figures and Tables

Sorry, we couldn't extract any figures or tables for this paper.

Slides referencing similar topics