A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects

@article{Kadayinti2017ACR,
  title={A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects},
  author={Naveen Kadayinti and Maryam Shojaei Baghini and Dinesh Kumar Sharma},
  journal={2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)},
  year={2017},
  pages={15-20}
}
Repeaterless low swing interconnects have been proposed for enhancing the performance of long on-chip inter-connects. Synchronization of these high speed, low swing inter-connects is important for proper operation. This paper discusses a clock synchronizing circuit for low swing interconnects. The circuit uses a combination of a delay locked loop (DLL), that generates multiple phases of the clock, and an analog voltage controlled delay line (VCDL). The circuit picks one of the phases of the DLL… CONTINUE READING

Citations

Publications citing this paper.

References

Publications referenced by this paper.
SHOWING 1-10 OF 16 REFERENCES

Chapter 27 : CMOS Circuit Design, Layout, and Simulation, Third Edition

  • R Jacob Baker
  • 2010
1 Excerpt

Similar Papers

Loading similar papers…