A Classification Processor for a Support Vector Machine with Embedded DSP Slices and Block RAMs in the FPGA

Abstract

This paper presents an FPGA implementation of a Support Vector Machine (SVM) classification using the DSP slices and block RAMs in the Xilinx Virtex-6 family FPGA. In our approach, the SVM classification is performed by the multiple DSPs. Our implementation supports 3 types of kernel functions, the sigmoid kernel, the polynomial kernel, and the RBF kernel. We connect DSPs with the built-in cascade logic in a DSP slice. Thus, our architecture consists of a cascaded DSP pipeline and process the input data with this pipeline. The number of DSP slices included in this cascade connection is equal to the number of the support vectors in the SVM. We have implemented the processor core which includes 768 DSPs for SVM classification in a Xilinx Virtex-6 FPGA XC6VLX240T-FF1156. The implementation results show that it can be implemented in the FPGA with 768 DSP48E1 slices, 800 block RAMs and 17680 slices. It runs in 370.096MHz clock frequency and can evaluate the SVM classification for 128-dimensional feature space data 2.89&#x00D7;10<sup>6</sup> times per second.

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Cite this paper

@article{Ago2013ACP, title={A Classification Processor for a Support Vector Machine with Embedded DSP Slices and Block RAMs in the FPGA}, author={Yuki Ago and Koji Nakano and Yasuaki Ito}, journal={2013 IEEE 7th International Symposium on Embedded Multicore Socs}, year={2013}, pages={91-96} }