Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18 µm CMOS Analog-to-Digital Convertor
This work proposes a 10b 170MS/s 0.18um CMOS pipeline ADC based on a double-channel op-amp sharing scheme to minimize power consumption. All the amplifiers of the ADC are continuously processing dual-channel signals regardless of clock phases. The measured differential and integral nonlinearities of the ADC are less than 0.31LSB and 0.72LSB. The prototype ADC with an active die area of 1.28mm shows a maximum SNDR of 53.1dB and consumes 47.9mW at 170MS/s and 1.8V.