A Cache Related Preemption Delay Analysis for Multi-level Non-inclusive Caches


domain. Assume thatM represents the set of all memory blocks and Dc captures the set of inclusion patterns of a memory block in a two-level cache hierarchy. The domain of the analysis (D) is the set of all valid mappings fromM to Dc as follows. D : M → (Dc ∪ {⊤}) (1) ACM Transactions on Embedded Computing Systems, Vol. V, No. N, Article A, Publication date… (More)


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