A CMOS high-frequency and low-voltage tunable positive transconductor with a improved linearization technique

@article{Pozo2007ACH,
  title={A CMOS high-frequency and low-voltage tunable positive transconductor with a improved linearization technique},
  author={J.M.G. del Pozo and P. A. Mart{\'i}nez Mart{\'i}nez and Ar{\'a}nzazu Ot{\'i}n and Nicol{\'a}s Medrano},
  journal={2007 50th Midwest Symposium on Circuits and Systems},
  year={2007},
  pages={177-180}
}
In this paper we present a high frequency and low- voltage positive tunable CMOS transconductor using low cost 0.35 mum CMOS technology. The system works with 2.2 V supply voltage achieving operation frequencies and transconductances higher than 2 GHz and 750 muS. The circuit has been designed with an improved linearization technique based on the parallel of an NMOS transistor in saturation with another NMOS transistor in triode region. 

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