A CMOS digital PLL with improved locking

Abstract

A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector (DPFD) is presented. The self-calibration technique is employed to acquire fast acquisition, low-jitter and wide frequency range. The DPLL works from 60 to 600 MHz with a maximum power consumption of 3.5mW at a supply voltage of 1.8V. It also features a fractional-N… (More)

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