A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability

@inproceedings{Jovanovic2011ACV,
  title={A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability},
  author={Goran S. Jovanovic and Mile K. Stojcev and Zoran Stamenkovic},
  year={2011}
}
A CMOS voltage controlled ring oscillator based on N-stage single-ended chain of different inverter types is described in this paper. The proposal is characterized by increased frequency stability (∆ f/ f < 2%) in term of power supply voltage variations in respect to standard solutions (∆ f/ f > 4%). The presented results are obtained using HSpice simulation and CMOS library model, level 49, for 1.2 μm technology. 
Highly Cited
This paper has 25 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 20 extracted citations

Output encoding for cochlear signal analysis

2015 IEEE Biomedical Circuits and Systems Conference (BioCAS) • 2015
View 13 Excerpts
Highly Influenced

A supply-insensitive self-regulating CMOS ring oscillator

2015 International SoC Design Conference (ISOCC) • 2015
View 3 Excerpts
Highly Influenced

Power efficient voltage controlled oscillator design in 180nm CMOS technology

2017 International Conference on Computing, Communication and Automation (ICCCA) • 2017

A power efficient phase frequency detector and low mismatch charge pump in on-chip clock generator

2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER) • 2016
View 1 Excerpt

References

Publications referenced by this paper.
Showing 1-10 of 13 references

STOJČEV, A Method for Improvement Stability of a CMOS Voltage Controlled Ring Oscillators

M. G. JOVANOVIĆ
ICEST • 2007
View 1 Excerpt

Current starved delay element with symmetric load

G. JOVANOVIĆ, M. STOJČEV
International Journal of Electronics, Vol. 93, 3, • 2006
View 2 Excerpts

A Method to Derive an Equation for the Oscillation Frequency of a Ring Oscillator

S. Docking, M. Sachdev
IEEE Trans. on Circuits and Systems - I: Fundamental Theory and Applications, vol. 50, 2, • 2003
View 2 Excerpts

A Power-Efficient Wide-Range Phase-Locked Loop

O.-C. CHEN, R. SHEEN
IEEE Journal of Solid State Circuits, vol.37, 1, • 2002
View 2 Excerpts

B

C. H. PARK, O. KIM
KIM, A 1.8-GHz self-calibrated phase locked loop with precise I/Q matching, IEEE J. Solid-State Circuits, vol. 36, • 2001
View 2 Excerpts

KWASNIEWSKI, A 1.25-GHz 0.35- m monolithic CMOS PLL based on a multiphase ring oscillator

L SUNT.A.
IEEE J. Solid-State Circuits, • 2001
View 1 Excerpt

A 10-Gb/s CMOS clock and data recovery circuit

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) • 2000
View 1 Excerpt

Similar Papers

Loading similar papers…