A CMOS Design Strategy for Bit-Serial Signal Processing

@article{Murray1985ACD,
  title={A CMOS Design Strategy for Bit-Serial Signal Processing},
  author={A T Murray and P. Denyer},
  journal={IEEE Journal of Solid-State Circuits},
  year={1985},
  volume={20},
  pages={746-753}
}
We present a summary of the features and successes of a Silicon Compiler (FIRST) for LSI nMOS bit-serial signal processors. A replacement cell library of CMOS operators has been designed for the compilation of true VLSI bit-serial signal processors. The cell library is implemented in 2.5-/spl mu/m buIk CMOS technology, and maintains a consistent performance of 20 MHz. We describe the design philosophy and style behind the CMOS cells, detailing the dynamic logic style used, its layout and… CONTINUE READING

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