A CMOS Classifier Circuit Using Neural Networks With Novel Architecture

Abstract

In this letter, complementary metal-oxide-semiconductor (CMOS) implementation of a neural network (NN) classifier with several output levels and a different architecture is given. The proposed circuit operates in current mode and can classify several types of data. The classifier circuit is designed using a current-voltage converter, an inverter followed by a NOR gate and a voltage-current output stage. Using a 0.35-m TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the expected results.

DOI: 10.1109/TNN.2007.902961

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Cite this paper

@article{Yildiz2007ACC, title={A CMOS Classifier Circuit Using Neural Networks With Novel Architecture}, author={Merih Yildiz and Shahram Minaei and Izzet Cem G{\"{o}knar}, journal={IEEE Transactions on Neural Networks}, year={2007}, volume={18}, pages={1845-1850} }