A CMOS 6b 400 M sample/s ADC with error correction

@article{Tsukamoto1998AC6,
  title={A CMOS 6b 400 M sample/s ADC with error correction},
  author={Shuya Tsukamoto and Toshiaki Endo and W M Schofield},
  journal={1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)},
  year={1998},
  pages={152-153}
}
Applications of A/D converters (ADC) in digital data reading, for example hard disk drives (HDD), digital video disk, and 10BaseT, require high speed and low error rate. Short latency is also important for HDD applications that have feedback loops. Most error correction techniques detect at thermometer code zero-to-one transition to reject bubbles (sparkle errors). These techniques require many elements, making high-speed operation difficult in CMOS. This paper describes a CMOS ADC with 2-clock… CONTINUE READING

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