A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy

@inproceedings{Li2003ABS,
  title={A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy},
  author={Jin-Fu Li and Jen-Chieh Yeh and Rei-Fu Huang and Cheng-Wen Wu and Peir-Yuan Tsai and Archer Hsu and Eugene Chow},
  booktitle={ITC},
  year={2003}
}
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Efficient yield-enhancement techniques for embedded memories thus are important for SOC. In this paper we present a built-in self-repair (BISR) scheme for semiconductor memories with 2-D redundancy structures. The BISR design is composed of a built-in self-test (BIST) module… CONTINUE READING
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