A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy

Abstract

Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed memory hierarchy enhancements for coherence traffic reduction and prefetching suggest that additional useful patterns emerge with a macroscopic, coarse-grain view. This paper presents RegionTracker, a dual-grain, on… (More)
DOI: 10.1109/L-CA.2007.9

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@article{Zebchuk2007ABB, title={A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy}, author={Jason Zebchuk and Andreas Moshovos}, journal={IEEE Computer Architecture Letters}, year={2007}, volume={6}, pages={33-36} }