A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture

@article{Nakajima2010ABS,
  title={A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture},
  author={Yuji Nakajima and Akemi Sakaguchi and Toshio Ohkido and Norihito Kato and Tetsuya Matsumoto and Michio Yotsuyanagi},
  journal={IEEE Journal of Solid-State Circuits},
  year={2010},
  volume={45},
  pages={707-718}
}
We have developed a 6b 2.7 GS/s folding ADC with on-chip background self-calibration in 90 nm CMOS technology. The ADC achieves high-speed operation of 2.7 GS/s at low power consumption of 50 mW from a 1.0 V power supply and the figure of merit (FOM) is 0.47 pJ/conversion-step. The key technique is a digital background self-calibration architecture which compensates for the large mismatch of small devices in the ADC and also corrects the ADC characteristics degradation during operation due to… CONTINUE READING

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Key Quantitative Results

  • It reduces the overall analog power of our design by 50%, compared with a conventional architecture which applies calibration only to preamplifiers.

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