A BIST Architecture For At-Speed DRAM Testing

@inproceedings{Huang2001ABA,
  title={A BIST Architecture For At-Speed DRAM Testing},
  author={Shi-Yu Huang and Ding-Ming Kwai and Chris Chu Cheng Huang},
  year={2001}
}
A high-speed Built-In Self-Test (BIST) architecture for Dynamic Random Access Memories (DRAMs) is proposed. The circuit automatically generates a sequence of pre-defined test patterns for on-chip DRAM testing. The innovation herein is mainly an architecture consisting of two finite state machines, instead of the conventional single finite state machine. Based upon this architecture, the pipeline technique can then be applied to divide the pattern generation process into stages, leading to a… CONTINUE READING

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