# A BDD-Based Approach to Constructing LFSRs for Parallel CRC Encoding

@article{Dubrova2012ABA, title={A BDD-Based Approach to Constructing LFSRs for Parallel CRC Encoding}, author={Elena Dubrova and Shohreh Sharif Mansouri}, journal={2012 IEEE 42nd International Symposium on Multiple-Valued Logic}, year={2012}, pages={128-133} }

Cyclic Redundancy Check codes (CRC) are widely used in data communication and storage devices for detecting burst errors. In applications requiring high-speed data transmission, multiple bits of an CRC are computed in parallel. Traditional methods for constructing an Linear Feedback Shift Register (LFSR) generating k bits of an CRC in parallel are based on computing kth power of the connection matrix of the LFSR. We propose an alternative method which is based on computing kth power of the…

## 10 Citations

An Algorithm for Constructing a Smallest Register with Non-Linear Update Generating a Given Binary Sequence

- Computer Science, MathematicsArXiv
- 2013

Expected size of RNLUs constructed by the presented algorithm is proved to be O(n/log( n/p), where n is the sequence length and p is the degree of parallelization.

An Algorithm for Constructing a Minimal Register with Non-linear Update Generating a Given Sequence

- Mathematics, Computer Science2014 IEEE 44th International Symposium on Multiple-Valued Logic
- 2014

Expected size of RNLUs constructed by the presented algorithm is proved to be asymptotically smaller than the expected size of TSPs constructed by previous algorithms generating the same sequence.

Ternary cyclic redundancy check by a new hardware-friendly ternary operator

- Computer ScienceMicroelectron. J.
- 2016

CRC-Based Message Authentication for 5G Mobile Technology

- Computer Science2015 IEEE Trustcom/BigDataSE/ISPA
- 2015

A new CRC-based message authentication method that enables combining the detection of random and malicious errors without increasing bandwidth and provides a quantitative analysis of the achieved security as a function of message and CRC sizes is presented.

CRC-Based Message Authentication for 5G Mobile Technology

- Computer ScienceTrustCom 2015
- 2015

A new CRC-based message authentication method that enables combining the detection of random and malicious errors without increasing bandwidth and provides a quantitative analysis of the achieved security as a function of message and CRC sizes is presented.

A novel pseudo random number generator based on L'Ecuyer's scheme

- Computer Science2014 11th International Conference on Security and Cryptography (SECRYPT)
- 2014

This scheme, despite the very simple functions on which it relies on, is strongly secure in the sense that its number sequences pass the state-of-the-art randomness tests and, importantly, an accurate and deep security analysis shows that it is resistant to a number of attacks.

Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors

- Computer ScienceIEEE Transactions on Computers
- 2014

This work proposes a scalable, highly accurate method to estimate working set size (WSS) of an application, and demonstrates the use of TWSS to switch-off the over-allocated cache ways in Static and Dynamic NonUniform Cache Architectures (SNUCA, DNUCA) on a tiled CMP.

Co-Locating Code and Data for Energy-Efficient CPUs

- Computer Science
- 2016

A data prefetcher called Tempo is designed that reduces useless prefetches by 18% and increases timeliness by 43% and an execution paradigm called Anti-Fetching, which dynamically moves code off-chip to a Near-Data Processor is described.

## References

SHOWING 1-10 OF 39 REFERENCES

A Systematic Approach for Parallel CRC Computations

- Computer ScienceJ. Inf. Sci. Eng.
- 2001

The approach is to systematically decompose the original input message into a set of subsequences based on the theory of Galois field so that parallel CRC computations can be achieved by inputting those subsequences at the same time and employing the lookahead technique for those sequences to speedup computation.

Application of LFSRs for Parallel Sequence Generation in Cryptologic Algorithms

- Computer ScienceICCSA
- 2006

It is shown that sequences generated by linear feedback shift registers (LFSRs) can be tailored to suit the appropriate algorithms, and this reduces both time and chip area for hardware implementation.

On Analysis and Synthesis of (n,k)-Non-Linear Feedback Shift Registers

- Mathematics, Computer Science2008 Design, Automation and Test in Europe
- 2008

(n,k)-NLFSRs are introduced which can be considered a generalization of the Galois type of LFSR and demonstrate that they are capable of generating output sequences with good statistical properties which cannot be generated by the Fibonacci type of NLFSRs.

Parallel CRC Realization

- Computer ScienceIEEE Trans. Computers
- 2003

This paper has identified a recursive formula from which their parallel implementation is derived and developed high-level parametric codes that are capable of generating the circuits autonomously when only the polynomial is given.

Parallel CRC generation

- Computer ScienceIEEE Micro
- 1990

A method of designing hardware parallel encoders for CRCs that is based on digital system theory and z-transforms is presented, which allows designers to derive the logic equations of the parallel encoder circuit for any generator polynomial.

Application of LFSRs in Time/Memory Trade-Off Cryptanalysis

- Computer ScienceWISA
- 2005

This work suggests the use of LFSR sequences for function generation to be used in the rainbow TMTO, and shows that there are functions for which the counter method fails.

Shift Register Sequences

- Computer Science
- 1981

The Revised Edition of Shift Register Sequences contains a comprehensive bibliography of some 400 entries which cover the literature concerning the theory and applications of shift register sequences.

Synthesis of parallel binary machines

- Computer Science, Mathematics2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
- 2011

An algorithm for synthesis of binary machines with the minimum number of stages for a given degree of parallelization is presented, showing that for sequences with high linear complexity such as complementary, Legendre, or truly random, parallel binary machines are an order of magnitude smaller than parallel FSRs generating the same sequence.

High-speed parallel CRC circuits in VLSI

- Computer ScienceIEEE Trans. Commun.
- 1992

It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should still enable current CMOS technologies to go well beyond 1 Gb/s data rates.

A high-performance CMOS 32-bit parallel CRC engine

- Computer Science
- 1999

Design highlights for a 32-bit parallel cyclic redundancy check (CRC) generator engine are presented and a compact layout is achieved by predecoding eight groups of four bits followed by performing a binary tree reduction on nets that are sorted by fanout.