A 940 MHz data rate 8 Mb CMOS SRAM

@article{Braceras1999A9M,
  title={A 940 MHz data rate 8 Mb CMOS SRAM},
  author={Geordie Braceras and Alun Roberts and Reid Wistort and Todd Frederick and Martin P. Robillard and S. Hall and S. G. Burns and Manuela Graf},
  journal={1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)},
  year={1999},
  pages={198-199}
}
An 8 Mb CMOS SRAM cycles at 470 MHz and provides a data rate of 940 MHz when run in the double-data rate (DDR) mode. Improved redundancy minimizes SRAM latency, enabling 3.4 ns access time. The HSTL I/O performance is enhanced by using flip-chip C4 packaging and by decoupling the I/O supply on-chip. The 8 Mb SRAM has an architecture to allow both /spl times/18 and /spl times/36 organizations, as well as a 4 Mb cut-down. 
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A 300MHz, 3.3V 1Mb SRAM Fabricated in a 0.5pm CMOS Process,

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