A 90-nm logic technology featuring strained-silicon

  title={A 90-nm logic technology featuring strained-silicon},
  author={S. Thompson and Mark Armstrong and Chris Auth and Marjan Alavi and Martin Buehler and R. S. Chau and S. M. Cea and Tahir Ghani and Grant Glass and Thomas Hoffman and C.-H. Jan and Cynthia L Kenyon and Jason Klaus and Kelin J. Kuhn and Zhiyong Ma and B. Mcintyre and K. Mistry and Anand Murthy and Borna Obradovic and R. Nagisetty and Phi Nguyen and Sam Sivakumar and Reaz Shaheed and Lucian Shifren and Bruce J. Tufts and Shweta Tyagi and M. Bohr and Y. El-Mansy},
  journal={IEEE Transactions on Electron Devices},
A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive… CONTINUE READING
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