A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter


This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock is made possible with almost no penalty in phase noise performance thanks to the use of a 10 bit, 0.55 ps/LSB digital-to-time converter (DTC) circuit operating on the sampling clock. The performance limitations of a practical DTC implementation are considered, and… (More)


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