A 9-bit, 14 μW and 0.06 mm $^{2}$ Pulse Position Modulation ADC in 90 nm Digital CMOS

@article{Naraghi2010A91,
  title={A 9-bit, 14 μW and 0.06 mm \$^\{2\}\$ Pulse Position Modulation ADC in 90 nm Digital CMOS},
  author={Shahrzad Naraghi and Matthew Courcy and Michael P. Flynn},
  journal={IEEE Journal of Solid-State Circuits},
  year={2010},
  volume={45},
  pages={1870-1880}
}
This work presents a compact, low-power, time-based architecture for nanometer-scale CMOS analog-to-digital conversion. A pulse position modulation ADC architecture is proposed and a prototype 9 bit PPM ADC incorporating a two-step TDC scheme is presented as proof of concept. The 0.06 mm2 prototype is implemented in 90 nm CMOS and achieves 7.9 effective bits across the entire input bandwidth and dissipates 14 μW at 1 MS/s. 
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