A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register

@article{Kim2014A9B,
  title={A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register},
  author={KwangSeok Kim and Wonsik Yu and Seonghwan Cho},
  journal={IEEE Journal of Solid-State Circuits},
  year={2014},
  volume={49},
  pages={1007-1016}
}
In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For pipelined operation, a novel time-register is proposed which is capable of storing, adding and subtracting time information with a clock signal. Together with a pulse-train time-amplifier, a 9-bit synchronous pipelined TDC is implemented, which consists of three 2.5 b/stage TDCs and a 3 b delay-line TDC. A prototype chip fabricated in 65 nm CMOS process achieves 1.12 ps of time resolution at 250 MS/s while… CONTINUE READING
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