An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS
This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock is made possible with almost no penalty in phase noise performance thanks to the use of a 10 bit, 0.55 ps/LSB digital-to-time converter (DTC) circuit operating on the sampling clock. The performance limitations of a practical DTC implementation are considered, and techniques for minimizing these limitations are presented. For example, background calibration guarantees appropriate DTC gain, reducing spurs. Operating at 10 GHz the system achieves −38 dBc of integrated phase noise (280 fs RMS jitter) when a worst case fractional spur of −43 dBc is present. In-band phase noise is at the level of −104 dBc/Hz. The class-B VCO can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9 V and 1.8 V supplies.