A 833 Mb/s 2.5 V 4 Mb double data rate SRAM

Abstract

A double-data-rate (DDR) SRAM overcomes the limitation of a single-data-rate (SDR) SRAM. The main features are an auto-tracking bitline scheme to reduce core cycle time, a shortened main data line for current reduction, a noise immune circuit having high-speed transfer characteristics through a dual-rail reset dynamic circuit, a two bit pre-fetched… (More)

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Cite this paper

@article{Park1998A8M, title={A 833 Mb/s 2.5 V 4 Mb double data rate SRAM}, author={H.-C. Park and S. K. Yang and M. S. Jung and T.-G. Kang and S.-C. Kim and K.-M. Sohn and D.-G. Bae and S. W. Kim and K. C. Kim and B.-S. Sohn and H.-S. Kim and H.-G. Byun and Y.-S. Shin and H.-K. Lim}, journal={1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)}, year={1998}, pages={356-357} }