A 800Mb/s/pin 2GB DDR2 SDRAM using an 80nm triple metal technology

@article{Kyung2005A82,
  title={A 800Mb/s/pin 2GB DDR2 SDRAM using an 80nm triple metal technology},
  author={Kye Hyun Kyung and Chi Wook Kim and Jae Young Lee and Jeong Hoon Kook and Sung Min Seo and Du Yeul Kim and Jun Hyung Kim and Jung Sunwoo and Hi Choon Lee and Chul Soo Kim and Byung Hoon Jeong and Young Soo Sohn and Sang Pyo Hong and Jae Hyung Lee and Jei Hwan Yoo and Soo in Cho},
  journal={ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.},
  year={2005},
  pages={468-610 Vol. 1}
}
A 1.8V, 800Mbit/s/pin, 2GB DDR2 SDRAM is developed using an 80nm triple metal technology. With the triple metal technology, NMOS precharge I/O scheme and statistical analysis, DDR800 4-4-4 performance is achieved at 1.8V. For mass production, a high-speed clock using an on chip PLL and an address-pin-reduction mode are employed. 

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A 1.8V, 700Mb/s/pin, 512Mb DDR-II SDRAM with On-Die Termination and Off-Chip Driver Calibration

  • C. Yoo
  • IEEE J. of Solid-State Circuits, pp. 941-951…
  • 2004
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