A 80/20 MHz 160 mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications

@article{Yoon2001A8M,
  title={A 80/20 MHz 160 mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications},
  author={Chi-Weon Yoon and Ramchan Woo and Jeonghoon Kook and Se-Joong Lee and Langmin Lee and Young-Don Bae and In-Cheol Yong Park and Hoi-Jun Yoo},
  journal={2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)},
  year={2001},
  pages={142-143}
}
An 84 mm/sup 2/ 160 mW programmable processor in 0.18 /spl mu/m EMC technology consists of 32 b RISC with MAC, 20 MHz motion compensation accelerator for MPEG-4 at SP, 3D rendering engine with 2.2 M polygon/s at 20 MHz, and 7.125 Mb embedded DRAM with single bitline writing scheme. 
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