A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip

@article{Chang2007A7D,
  title={A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip},
  author={Hsiu-Cheng Chang and Jiawei Chen and Ching-Lung Su and Yao-Chang Yang and Yao Li and Chun-Hao Chang and Ze-Min Chen and Wei-Sen Yang and Chien-Chang Lin and Ching-Wen Chen and Jinn-Shyan Wang and Jiun-In Guo},
  journal={2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  year={2007},
  pages={280-603}
}
A dynamic quality-scalable H.264 video encoder is presented for power-adaptive video encoding. In 0.13mum CMOS technology, it requires 470kgates/13.3kB SRAM and consumes 7mW/183mW in encoding 30fps CIF/HD720 video. Compared to the state-of-the-art design for real-time HD720 video encoding, a 49% reduction in gate count and a 61% reduction in internal memory is achieved 

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  • Compared to the state-of-the-art design for real-time HD720 video encoding, a 49% reduction in gate count and a 61% reduction in internal memory is achieved.

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ISO/IEC 14496-10

  • Joint Video Team of ISOIEC MPEG, ITU-T VCEG
  • .
  • 2003
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