A 76 dBΩ, 2mW, 10Gbps optical receiver analog front-end in 80nm CMOS


This paper describes the design of an optical receiver analog front end for a low power, high speed, chip-to-chip or board-to-board communication system. The circuit has been designed in 80 nm CMOS and consumes 2 mW with a 1-V supply. Using active inductors, a transimpedance gain of 62.5 dB-Omega, limiting amplifier gain of 15 dB, and overall bandwidth of 9… (More)

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