A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST

@article{Sakakibara2003A71,
  title={A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST},
  author={Hitomi Sakakibara and Michiaki Nakayama and Masanori Kusunoki and Katsumi Kurita and Hirofumi Otori and Masaichi Hasegawa and Shizue Iwahashi and Keiichi Higeta and Tsuneto Hanashima and Hiroo Hayashi and K. Kuchimachi and Katsutoshi Uehara and Takayuki Nishiyama and Masaji Kume and Kenji Miyamoto and Eiki Kamada},
  journal={2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.},
  year={2003},
  pages={458-508 vol.1}
}
A 750MHz 144Mb cache DRAM LSI incorporates speed-scalable embedded DRAM and SRAM macros, and is realized using a logic-merged DRAM process. The LSI has a built-in at-speed test engine with programmable test pattern and timing, merging logic and memory test. The die area is 285mm/sup 2/ in a 0.18/spl mu/m 6M logic-merged DRAM process. 
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