A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology

Abstract

The design and experimental verification of a 75-GHz phase-locked loop (PLL) fabricated in 90-nm CMOS technology is presented. The circuit incorporates a three-quarter wavelength oscillator to achieve high-frequency operation and a novel phase-frequency detector (PFD) based on SSB mixers to suppress the reference feedthrough. The PLL demonstrates an… (More)

20 Figures and Tables

Topics

Statistics

05101520082009201020112012201320142015201620172018
Citations per Year

80 Citations

Semantic Scholar estimates that this publication has 80 citations based on the available data.

See our FAQ for additional information.

  • Presentations referencing similar topics